1. Field of the Invention
This invention relates to the general area of data integrity in digital computers. More specifically it relates to reliable systems which use parity on a system data bus and error correcting code (ECC) memory.
2. Description of the Related Art
Parity checking is a method of verifying the integrity of digital data in a computer system. Parity checking is used to verify correct transmission of digital data over a system data bus which connects components of the computer system.
Parity checking is typically implemented by adding a single bit, called a "parity bit", to every byte (eight bits) of data transmitted on the system data bus, thus forming a nine bit parity word. This parity bit is used to "set" the total number bits in the nine bit parity word that are equal to "1" to an even or odd value. Even parity systems set the parity bit equal to "1" if there are an odd number of "set" bits in the associated byte. If there are an even number of bits equal to"1" in the associated byte, the parity bit is set to "0". This insures that there will always be an even number bits set equal to "1" within the nine bit parity word. Odd parity checking is implemented in an opposite manner.
Parity checking allows detection of an odd number of data transmission errors. Thus, if one of the bits in the nine bit parity word is transposed (from "1" to "0" or "0" to "1") during transmission, the total number of bits set equal to "1" will no longer be even or odd whichever it was originally, and the error can thus be detected. Although parity checking allows the detection of an odd number of errors, it does not allow correction of errors.
Error correcting codes (ECC) is a method of adding enough redundancy to a digital data word to allow the word to be reconstructed if one of its bits is errantly modified. ECC is typically used in large memory systems which have millions or billions of bits. In such systems, even with very low bit error rates, the number of bits present makes the probability of a bit error high.
ECC is typically implemented by adding seven bits to a thirty-two bit data word. These seven bits are called a syndrome. By adding the syndrome to a thirty-two bit data word it is possible to correct all single bit errors and detect all two bit errors. This is well known in the art and described in detail in the Bell System Technical Journal Volume XXIX, April 1950, Number 2 entitled "Error Detecting and Correcting Codes" by R. W. Hamming.
In order to make a computer system reliable, it is desirable to provide parity checks on the data which is transferred across the system bus. It is also desirable to provide ECC checks on the memory. In some instances, it is therefore required to convert from ECC syndrome to parity checking and back.
A problem associated with converting from ECC to parity checking is that an ECC checker/correcter can modify data words read from memory to correct single bit errors, and the parity on the system data bus must be generated from these corrected data words. Current systems perform the operations of ECC error checking and correction parity generation sequentially. The ECC unit checks and corrects the memory read data and the parity generation unit then generates parity on the corrected data for transmission onto the system bus. This serial operation takes a long time to perform and increases the memory latency which is the amount of time the system requires to access memory. Increasing memory latency always reduces the performance of the system.
The present invention overcomes this performance problem by utilizing a computer system to correct single bit errors in data words in parallel with the generation of appropriate parity bits.